New PDF release: A Combined Data and Power Management Infrastructure: For

By Jens Eickhoff (auth.), Jens Eickhoff (eds.)

ISBN-10: 3642355560

ISBN-13: 9783642355561

ISBN-10: 3642355579

ISBN-13: 9783642355578

This e-book describes the improvement and layout of a different mixed info and tool administration infrastructure The use in small satellites offers a few specific specifications to the structures like strength failure robustness and dealing with of alternative different types of exterior analog and electronic interfaces. those requisites result in a useful merge among On Board desktop and the satellite's strength regulate and Distribution Unit, which leads to a really cutting edge layout or even a patent association. This booklet offers method engineers and college scholars with the technical wisdom as combine among technical brochure and a person guide.

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Fig. 1 OBC processorboard flight model in the mounting frame. /IRS, Uni Stuttgart Typical home computers do not implement an SBC as their Processor-Board. They will in most cases have a processor on a mother board with additional cards connected to the mother board for functions such as memory control and graphics processing for example. All computers have some basic requirements that are necessary for the computer to operate—requirements such as memory resources, interfaces including a keyboard and a monitor as well as communication interfaces such as Ethernet and USB.

Non-volatile memory is essential because it typically contains the operating system the processor will use when it boots on power-up. In a home PC the non-volatile memory is fulfilled by the boot EEPROM and the 2 The OBC Processor-Boards 31 hard disk drive though in recent years we are seeing more and more solid state devices take the place of a hard disk. Since there are no hard disk drives that are qualified to fly in space, the non-volatile memory in a satellite needs to be of the solid state variety.

Sleep Bit Implementation: The two Sleep Bits are implemented on the FM SBC using LEON3FT GPIO signals. Each one controls one bank of 2 MB of non-volatile memory. 1 explains these signals and identifies their default condition. 1 NVSLEEP GPIO assignments Signal name LEON3FT I/O GPIO assignment Reset value Description NVSLEEP0 NVSLEEP1 High High 2 MB Bank 0 Sleep bit 2 MB Bank 1 Sleep bit O O GPIO12 GPIO13 • NVMEM EDAC Implementation: The LEON3FT on chip EDAC has been enabled on the FM SBC. Refer to the LEON3FT Functional Manual for a full description of the EDAC for the PROM memory area.

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A Combined Data and Power Management Infrastructure: For Small Satellites by Jens Eickhoff (auth.), Jens Eickhoff (eds.)

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