By Michael J. Flynn, Wayne Luk
The subsequent new release of machine approach designers may be much less fascinated with info of processors and stories, and extra eager about the weather of a process adapted to specific purposes. those designers may have a basic wisdom of processors and different components within the approach, however the luck in their layout depends on the talents in making system-level tradeoffs that optimize the price, functionality and different attributes to satisfy software standards. This e-book presents a brand new therapy of laptop process layout, rather for System-on-Chip (SOC), which addresses the problems pointed out above. It starts with an international advent, from the high-level view to the bottom universal denominator (the chip itself), then strikes directly to the 3 major construction blocks of an SOC (processor, reminiscence, and interconnect). subsequent is an outline of what makes SOC detailed (its customization skill and the purposes that force it). the ultimate bankruptcy offers destiny demanding situations for approach layout and SOC possibilities.Content:
Chapter 1 advent to the platforms method (pages 1–38):
Chapter 2 Chip fundamentals: Time, region, energy, Reliability, and Configurability (pages 39–73):
Chapter three Processors (pages 74–122):
Chapter four reminiscence layout: System?on?Chip and Board?Based structures (pages 123–164):
Chapter five Interconnect (pages 165–207):
Chapter 6 Customization and Configurability (pages 208–245):
Chapter 7 software stories (pages 246–284):
Chapter eight what is subsequent: demanding situations forward (pages 285–312):
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Extra info for Computer System Design: System-on-Chip
From a design complexity point of view, this has the advantage of being a “universal” solution: One implementation fits all applications, although not necessarily equally well. So, while a great deal of design effort is required for such an implementation, the production quantities can be large enough to justify the costs. An alternative to this approach is clear. For specific applications, whose memory size can be bounded, we can implement an integrated memory SOC. 3). 16 Processors with memory off-die.
Two classes of execution variations can arise and affect the scheduled execution behavior: 1. delayed results from operations whose latency differs from the assumed latency scheduled by the compiler and 2. interruptions from exceptions or interrupts, which change the execution path to a completely different and unanticipated code schedule. Although stalling the processor can control a delayed result, this solution can result in significant performance penalties. The most common execution delay is a data cache miss.
Explain. 5. 9, suppose instruction #3 sets the CC (condition code that can be tested by following a branch instruction) at the end of WB and instruction #4 is the condition branch. Without additional hardware support, what is the delay in executing instruction #5 if the branch is taken and if the branch is not taken? 6. Suppose we have four different processors; each does 25% of the application. If we improve two of the processors by 10 times, what would be the overall application speedup? 7. Suppose we have four different processors and all but one are totally limited by the bus.
Computer System Design: System-on-Chip by Michael J. Flynn, Wayne Luk